In recent years, development of technology to reduce parasitic capacitance in order to enhance the performance of semiconductor elements has progressed. A Silicon on Sapphire (SOS) structure is a structure for achieving the technology to reduce this parasitic capacitance. A method for forming the SOS structure is described in Japanese Unexamined Patent Application Publication No. 2010-278337A and in Japanese Unexamined Patent Application Publication No. 2004-343359A. In Japanese Unexamined Patent Application Publication No. 2010-278337A, the SOS structure is formed by bonding a sapphire substrate and a Si layer intermediated by an oxide film. In addition, in Japanese Unexamined Patent Application Publication No. 2004-343359A, the surfaces of two substrates made of different materials are activated with an ion beam or a Fast Atom Beam (FAB) gun and then joined intermediated by an intermediate layer containing a metal.